74HC138PW,118

74HC138PW,118 is a 3-to-8 line inverting decoder/demultiplexer. It decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (active-low Y0 to active-low Y7). The device features three enable inputs (active-low E1, active-low E2 and E3). Every output will be HIGH unless active-low E1 and active-low E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. It features ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V).

• CMOS low power dissipation, high noise immunity
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Demultiplexing capability, multiple input enable for easy expansion
• Ideal for memory chip select decoding, active LOW mutually exclusive outputs
• CMOS level input, complies with JEDEC standards
• Supply voltage range from 2V to 6V
• Input leakage current is ±1μA maximum at (VI = VCC or GND; VCC = 5.5V)
• Supply current is 160μA maximum at (VI = VCC or GND; IO = 0A; VCC = 5.5V)
• Propagation delay is 225ns maximum at (VCC = 2V, Tamb = -40°C to +125°C)
• Operating temperature range from -40°C to +125°C, TSSOP16 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.