AD9524BCPZ-REEL7

AD9524 is a jitter cleaner and clock generator with 6 differential or 13 LVCMOS outputs. It provides a low-power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6GHz to 4.0GHz. This is defined to support the clock requirements for long-term evolution and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter clean-up to achieve the restrictive low-phase noise requirements necessary for acceptable data converter SNR performance. Application includes LTE and multicarrier GSM base stations, wireless and broadband infrastructure, medical instrumentation, clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, low jitter, low phase noise clock distribution, clock generation and translation for SONET, 10Ge, 10G FC and other 10Gbps protocols, forward error correction (G.710), high performance wireless transceivers, ATE and high performance instrumentation.

• Typical power dissipation configuration is 559mW (fVCXO=122.88 MHz single-ended, -40 to +85°C)
• Maximum input frequency is 400MHz (fVCXO=122.88 MHz single-ended, -40 to +85°C)
• Minimum input slew rate (OSC-IN) is 400V/µs (limit imposed for jitter performance, -40 to +85°C)
• Typical differential input resistance is 4.8Kohm (fVCXO=122.88MHz single-ended, -40°C to +85°C)
• Typical duty cycle is 50% (f <lt/> 500MHz, fVCXO=122.88MHz single-ended, -40°C to +85°C)
• Maximum supply sensitivity is 0.6mV/mV (change in output swing vs. VDD3-OUT[x:y], -40°C to +85°C)
• Common-mode output voltage range from 1.125 to 1.375V (output driver static, -40°C to +85°C)
• Typical gain is 45MHz/V (fVCXO=122.88MHz, -40°C to +85°C)
• 48-lead lead frame chip scale package [LFCSP-VQ]
• Temperature range from -40°C to +85°C

Notes

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party