AS7C1026B-12JCN

AS7C1026B-12JCN is a 5V 64K X 16 CMOS SRAM. It is a high-performance CMOS 1,048,576-bit static random access memory (SRAM) device organized as 65,536 words ×16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. When active-low CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. Active-low LB controls the lower bits, I/O0 through I/O7, and active-low UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply.

• Organization: 65,536 words × 16 bits, 12ns access time
• Center power and ground pins for low noise
• Low power consumption: 605mW/max at 10ns (active), 55mW/max CMOS I/O (standby)
• 6 T 0.18 u CMOS technology
• Easy memory expansion with active-low CE, active-low OE inputs
• TTL-compatible, three-state I/O, JEDEC standard packaging
• ESD protection is ≥ 2000volts
• Latch-up current is ≥ 200mA
• Plastic SOJ, 400 mil package
• Commercial temperature range from 0 to 70°C